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a adf4001 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc. all rights reserved. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. rev. 200 mhz clock generator pll functional block diagram rf in a rf in b 13-bit n counter lock detect current setting 1 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 m1 m3 m2 sd out av dd ref in clk data le av dd dv dd v p cpgnd r set 14-bit r counter r counter latch function latch 24-bit input register n counter latch sd out 22 14 adf4001 muxout mux high z current setting 2 charge pump cp ce agnd dgnd phase frequency detector reference 13 features 200 mhz bandwidth 2.7 v to 5.5 v power supply separate charge pump supply (v p ) allows extended tuning voltage in 5 v systems programmable charge pump currents 3-wire serial interface hardware and software power-down mode analog and digital lock detect hardware compatible to the adf4110/adf4111/ adf4112/adf4113 typical operating current 4.5 ma ultralow phase noise 16-lead tssop 20-lead lfcsp applications clock generation low frequency plls low jitter clock source clock smoothing frequency translation sonet, atm, adm, dslam, sdm general description the adf4001 clock generator can be used to implement c lock sources for plls that require very low noise, stable refer ence signals. it consists of a low noise digital pfd (phase frequency detector), a precision charge pump, a programmable r eference divider, and a programmable 13-bit n counter. in add ition, the 14-bit reference counter (r counter) allows selectable ref in frequencies at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthesizer is used with an exter- nal loop filter and vco (voltage controlled oscillator) or vcxo (voltage controlled crystal oscillator). the n minimum value of 1 allows flexibility in clock generation. 2013 781/461-3113 b
rev. ? adf4001?pecifications 1 (av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6.0 v ; agnd = dgnd = cpgnd = 0 v; r set = 4.7 k ; t a = t min to t max , unless otherwise noted; dbm referred to 50 .) parameter b version unit test conditions/comments rf characteristics (3 v) see figure 3 for input circuit rf input frequency 5/165 mhz min/max rf input sensitivity ?0/0 dbm min/max rf characteristics (5 v) rf input frequency 10/200 mhz min/max ?/0 dbm min/max 20/200 mhz min/max ?0/0 dbm min/max ref in characteristics see figure 2 for input circuit ref in input frequency 5/104 mhz min/max for f < 5 mhz, use dc-coupled square wave (0 to v dd ) ref in input sensitivity 2 ? dbm min ac-coupled. when dc-coupled: 0 to v dd max (cmos compatible) ref in input capacitance 10 pf max ref in input current 100 a max phase detector phase detector frequency 3 55 mhz max charge pump i cp sink/source programmable: see table v high value 5 ma typ with r set = 4.7 k ? low value 625 a typ absolute accuracy 2.5 % typ with r set = 4.7 k ? r set range 2.7/10 k ? typ see table v i cp three-state leakage current 1 na typ sink and source current matching 2 % typ 0.5 v v cp v p ?0.5 i cp vs. v cp 1.5 % typ 0.5 v v cp v p ?0.5 i cp vs. temperature 2 % typ v cp = v p /2 logic inputs v inh , input high voltage 0.8 dv dd v min v inl , input low voltage 0.2 dv dd v max i inh /i inl , input current 1 a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage dv dd ?0.4 v min i oh = 500 a v ol , output low voltage 0.4 v max i ol = 500 a power supplies av dd 2.7/5.5 v min/v max dv dd av dd v p av dd /6.0 v min/v max av dd v p 6.0 v i dd 4 (ai dd + di dd ) adf4001 5.5 ma max 4.5 ma typical i p 0.4 ma max t a = 25 c low power sleep mode 1 a typ noise characteristics adf4001 phase noise floor 5 ?61 dbc/hz typ @ 200 khz pfd frequency ?53 dbc/hz typ @ 1 mhz pfd frequency phase noise performance 6 @ vcxo output 200 mhz output 7 ?9 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency spurious signals 200 mhz output 7 ?0/?5 dbc typ/dbc typ @ 200 khz/400 khz and 200 khz pfd frequency notes 1 operating temperature range (b version) is ?0 c to +85 c. 2 av dd = dv dd = 3 v; for av dd = dv dd = 5 v, use cmos compatible levels. 3 guaranteed by design. sample tested to ensure compliance. 4 t a = 25 c; av dd = dv dd = 3 v; rf in = 100 mhz. 5 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 logn (where n is the n divider value). 6 the phase noise is measured with the eval-adf4001eb1 evaluation board and the hp8562e spectrum analyzer. 7 f ref in = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 200 mhz; n = 1000; loop b/w = 20 khz. specifications subject to change without notice. b
rev. ? adf4001 timing characteristics limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth guaranteed by design but not production tested. specifications subject to change without notice. (av dd = dv dd = 3 v 10%, 5 v 10%; av dd v p 6.0 v ; agnd = dgnd = cpgnd= 0 v; r set = 4.7 k ; t a = t min to t max , unless otherwise noted; dbm referred to 50 .) t 1 t 2 t 3 t 4 t 6 t 5 db20 (msb) db19 db2 db1 (control bit c2) clock data le le db0 (lsb) (control bit c1) figure 1. timing diagram absolute maximum ratings 1, 2 ( t a = 25 c, unless otherwise noted.) av dd to gnd 3 . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +0.3 v v p to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v p to av dd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +5.5 v digital i/o voltage to gnd . . . . . . . . . ?.3 v to v dd + 0.3 v analog i/o voltage to gnd . . . . . . . . . . ?.3 v to v p + 0.3 v ref in , rf in a, rf in b to gnd . . . . . . . ?.3 v to v dd + 0.3 v rf in a to rf in b . . . . . . . . . . . . . . . . . . . . . . . . . . . . mv operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . . 150 c tssop ja thermal impedance . . . . . . . . . . . . . . 150.4 c/w lfcsp ja thermal impedance (paddle soldered) . . 122 c/w lfcsp ja thermal impedance (paddle not soldered) 216 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high performance rf integrated circuit with an esd rating of <2 k ? and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf4001 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device b 600
adf4001 rev. b | page 4 pin configurations tssop lfcsp table 1. pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 19 r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is set maxcp r i 5.23 ? so, with r set = 4.7 k, i cp max = 5 ma. 2 20 cp charge pump output. when enabled, this provides i cp to the external loop filter which, in turn, drives the external vco or vcxo. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the n counter. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. see figure 3. 6 5 rf in a input to the n counter. this small signal inp ut is ac-coupled to the external vco or vcxo. 7 6, 7 av dd analog power supply. this ranges from 2.7 v to 5.5 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must have the same value as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k. see figure 2. this input can be driven from a ttl or cmos crystal oscillator or can be ac-coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three-state mode. taking the pin high will power up the device, depending on the status of the power-down bit f2. 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected by using the control bits. 14 15 muxout this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd digital power supply. this ranges from 2.7 v to 5.5 v. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must be the same value as av dd . 16 18 v p charge pump power supply. this shou ld be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5 v and used to drive a vco or vcxo with a tuning range of up to 5 v. n/a ep epad exposed pad. the exposed pad should be connected to agnd. r set cp cpgnd agnd rf in b rf in a av dd ref in le muxout dv dd v p ce clk data dgnd notes 1. transistor count 6425 (cmos) and 50 (bipolar). top view (not to scale) 1 2 3 4 5 6 7 8 adf4001 16 15 14 13 12 11 10 9 02569-003 agnd muxout le data clk ce av dd av dd ref in dgnd dgnd cp r set v p dv dd dv dd cpgnd agnd rf in b rf in a notes 1. transistor count 6425 (cmos) and 50 (bipolar). 2. connect exposed pad to agnd. 14 13 12 1 3 4 15 11 2 5 7 6 8 9 1 0 1 9 2 0 1 8 1 7 1 6 adf4001 top view (not to scale) 02569-004
rev. ? t ypical performance characteristicsadf4001 frequency ?mhz 0 0 amplitude ?dbm ? ?0 ?5 ?0 ?5 ?0 ?5 50 100 150 200 250 t a = +25 c t a = +85 c t a = ?0 c tpc 1. input sensitivity, v dd = 3.3 v, 100 pf on rf in frequency ?mhz 0 0 amplitude ?dbm ? ?0 ?5 ?0 ?5 ?0 5101 52025 tpc 2. input sensitivity, v dd = 3.3 v, 100 pf on rf in 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 output power ?db ?khz ?khz 200mhz 1khz 2khz 0 reference level = ?.7dbm v dd = 3v, v p = 5v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds a verages = 26 ?9.2dbc/hz tpc 3. phase noise (200 mhz, 200 khz, 20 khz) frequency offset from 200mhz carrier ?hz ?0 100 phase noise ?dbc/hz ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 ?40 1k 10k 100k 1m 0.229 rms 10db/division r l = ?0dbc/hz rms noise = 0.229 degrees tpc 4. integrated phase noise (200 mhz, 200 khz, 20 khz) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 output power ?db ?00khz ?00khz 0 200mhz 100khz 200khz v dd = 3v, v p = 5v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 300hz video bandwidth = 300hz sweep = 4.2 seconds a verages = 20 reference level = ?.7dbm ?2.3dbc tpc 5. reference spurs (200 mhz, 200 khz, 20 khz) b
rev. adf4001 ? circuit description reference input section the reference input stage is shown in figure 2. sw1 and sw2 ar e normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. power-down control to r counter nc no sw1 sw3 sw2 nc 100k ref in bu ffer figure 2. reference input stage rf input stage the rf input stage is shown in figure 3. it is followed by a two-stage limiting amplifier to generate the cml clock levels needed for the n counter buffer. rf in b rf in a 2k agnd av dd bias generator 2k 1.6v figure 3. rf input stage n counter t he n cmos counter allows a wide ranging division ratio in the pll feedback counter. division ratios of 1 to 8191 are allowed. n and r relationship the n counter with the r counter make it pos sible to generate output frequencies that are spaced only by the reference fre- quency divided by r . the equation for the vco frequency is fnrf vco refin = f vco is the output frequency of the external voltage cotrolled oscillator (vco). n is the preset divide ratio of the binary 13-bit counter (1 to 8,191). f refin is the external reference frequency oscillator. r is the preset divide ratio of the binary 14-bit programmable reference counter (1 to 16,383). to pfd 13-bit n counter from n counter latch from rf input stage figure 4. n counter r counter the 14-bit r counter allows the input reference frequency to be d ivided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 5 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that no dead zone is in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the reference counter latch, abp2 and abp1, control the width of the pulse (see table iii). delay r divider n divider cp output hi hi cpgnd v p charge pump up cp down n divider r divider d1 q1 u1 clr1 d2 clr2 q2 u2 u3 figure 5. pfd simplified schematic and timing (in lock) muxout and lock detect the output multiplexer on the adf4001 family allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 in the function latch. table v shows the full truth table. figure 6 shows the muxout section in block diagram form. b
rev. adf4001 ? analog lock detect digital lock detect r counter output n counter output sdout dgnd dv dd control muxout mux figure 6. muxout circuit lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. when ldp in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecu tive p hase detector cycles is less than 15 ns. with ldp set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. it will stay set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be operated w ith an external pull-up resistor of 10 k ? nominal. when lock has been detected, this output will be high with narrow low-going pulses. input shift register the adf4001 digital section includes a 24-bit input shift regis- ter, a 14-bit r counter, and a 13-bit n counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs, db1 and db0, as shown in the timing diagram of figure 1. the truth table for these bits is shown in table i. table ii shows a sum- mary of how the latches are programmed. table i. c2, c1 truth table control bits c2 c1 data latch 00 r counter 01 n counter 10 function latch 11 initialization latch table ii. adf4001 family latch summary reference counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2r3r4r5 r7 r14 abp1 t2 ldp r13 r6 co ntrol bits abp2 t1 db21 r12 r11 r10 db22 db23 r8 r9 r eserved lock detect precision test mode bits anti- ba cklash width 14-bit reference counter xxx db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1m2m3 f3 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 co ntrol bits c ounter r eset p ower- d own 1 muxout co ntrol phase detector polarity cp three- state p ower- d own 2 c urrent se tting 1 ti mer counter co ntrol cpi3 cpi4 db21 c urrent se tting 2 tc3 tc2 tc1 db22 db23 fa stlock e nable fast lock mode f4 f5 r eserved x = don? care xx db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) n1 n8 n9 n12 n13 n7 g1 co ntrol bits n10 n11 db21 n6 n5 n4 db22 db23 n2 n3 r eserved cp gain r eserved 13-bit n counter xx xxxxxx db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1m2m3 f3 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 co ntrol bits c ounter r eset p ower- d own 1 muxout co ntrol phase detector polarity cp three- state p ower- d own 2 c urrent se tting 1 ti mer counter co ntrol cpi3 cpi4 db21 c urrent se tting 2 tc3 tc2 tc1 db22 db23 fa stlock e nable fast lock mode f4 f5 r eserved xx n counter latch function latch initialization latch b
rev. adf4001 ? table iii. reference counter latch map ldp operation 0t hree consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1f ive consecutive cycles of phase delay less than 15ns must occur before lock detect is set. abp2 abp1 antibacklash pulse width 002.9ns 011.3ns 106.0ns 112. 9ns r14 r13 r12 .......... r3 r2 r1 divide ratio 000 .......... 0011 000 .......... 0102 000 .......... 0113 000 .......... 1004 ... .......... .... ... .......... .... ... .......... .... 111 .......... 10016380 111 .......... 10116381 111 .......... 11016382 111 .......... 11116383 test mode bits should be set to 00 for normal operation db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2r3r4r5 r7 r14 abp1 t2 ldp r13 r6 cont rol bits abp2 t1 db21 r12 r11 r10 db22 db23 r8 r9 r eserved lock detect precision test mode bits anti- ba cklash width 14-bit reference counter xxx x = don? care b
rev. adf4001 ? table iv. n counter latch map these bits are not used by the device and are don? care bits. f4 (function latch) fa stlock enable cp gain operation 0 0c harge pump current setting 1 is permanently used 0 1c harge pump current setting 2 is permanently used 1 0c harge pump current setting 1 is used 1 1c harge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fastlock mode is used. see function latch description. n13 n12 n11 n3 n2 n1 n counter divide ratio 000 .......... 0011 000 .......... 0102 000 .......... 0113 000 .......... 1004 ... .......... .... ... .......... .... ... .......... .... 111 .......... 1008188 111 .......... 1018189 111 .......... 1108190 111 .......... 1118191 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) n1 n2n3 n4 n5 n6 n7 n8n9 n10 n11 n12 n13 control bits reserved 13-bit n counter db21 re served db22 db23 cp gain g1 x = don? care x x x xxx x x b
rev. adf4001 ?0 table v. function latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1m2m3 f3 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cont rol bits c ounter r eset p ower- d own 1 muxout cont rol phase detector polarity cp three- state p ower- d own 2 current se tting 1 timer counter cont rol cpi3 cpi4 db21 current se tting 2 tc3 tc2 tc1 db22 db23 fa stlock e nable fas tlock mode f4 f5 r eserved ce pin pd2 pd1 mode 0 xxa synchronous power-down 1x0norm al operation 101asy nchronous power-down 111sy nchronous power-down cpi6 cpi5 cp14 i cp (ma) cpi3 cpi2 cpi1 2.7k 4.7k 10k 000 1.088 0.625 0.294 001 2.176 1.25 0.588 010 3.264 1.875 0.882 011 4.352 2.5 1.176 100 5.44 3.125 1.47 101 6.528 3.75 1.764 110 7.616 4.375 2.058 111 8.704 5.0 2.352 time out tc4 tc3 tc2 tc1 (pfd cycles) 00003 00017 001011 001115 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 f4 f5 fastlock mode 0x fastlock disabled 10 fastlock mode 1 11 fastlock mode 2 f3 charge pump output 0n ormal 1t hree-state m3 m2 m1 output 000 three-state output 001d igital lock detect 010n di vider output 011av dd 100r di vider output 101 n-channel open-drain l ock detect 110se rial data output 111 dgnd phase detector f2 polarity 0ne gative 1pos itive counter f1 operation 0 normal 1 r, n counter held in reset x = don? care x x b
rev. adf4001 ?1 table vi. initialization latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1m2m3 f3 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cont rol bits c ounter r eset p ower- d own 1 muxout cont rol phase detector polarity cp three- state p ower- d own 2 current se tting 1 timer counter cont rol cpi3 cpi4 db21 current se tting 2 tc3 tc2 tc1 db22 db23 fa stlock e nable fast lock mode f4 f5 r eserved ce pin pd2 pd1 mode 0 xxa synchronous power-down 1x0norm al operation 101asy nchronous power-down 111sy nchronous power-down cpi6 cpi5 cp14 i cp (ma) cpi3 cpi2 cpi1 2.7k 4.7k 10k 000 1.088 0.625 0.294 001 2.176 1.25 0.588 010 3.264 1.875 0.882 011 4.352 2.5 1.176 100 5.44 3.125 1.47 101 6.528 3.75 1.764 110 7.616 4.375 2.058 111 8.704 5.0 2.352 time out tc4 tc3 tc2 tc1 (pfd cycles) 00003 00017 001011 001115 01001 9 01012 3 01102 7 01113 1 10003 5 10013 9 10104 3 10114 7 11005 1 11015 5 11105 9 11116 3 f4 f5 fastlock mode 0x fastlock disabled 10 fastlock mode 1 11 fastlock mode 2 f3 charge pump output 0n ormal 1t hree-state m3 m2 m1 output 000 three-state output 001d igital lock detect 010n di vider output 011av dd 100r di vider output 101 n-channel open-drain l ock detect 110se rial data output 111 dgnd phase detector f2 polarity 0ne gative 1pos itive counter f1 operation 0 normal 1 r, n counter held in reset x = don? care xx b
rev. adf4001 ?2 function latch with c2, c1 set to 1, 0, the on-chip function latch will be pro- grammed. table v shows the input data format for programming the function latch. counter reset d b2 (f1) is the counter reset bit. when this is 1, the r counter and the a, b counters are reset. for normal operation, this bit should be 0. upon powering up, the f1 bit needs to be disabled, and the n counter resumes counting in close alignment with the r counter. (the m aximum error is one prescaler cycle.) power-down db3 (pd1) and db21 (pd2) on the adf4001 family provide p rogrammable power-down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2, pd1. in the programmed asynchronous power-down, the device pow- ers down immediately after latching a 1 into bit pd1, with the condition that pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power- down is gated by the charge pump to prevent unwanted frequency jumps. o nce the power-down is enabled by writing a 1 into bit pd1 (on condition that a 1 has also been loaded to pd2), the device will go into power-down on the occurrence of the next charge pump event. when a power-down is activated (either synchronous or asyn- chronous mode, including ce pin activated power-down), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital clock detect circuitry is reset. ? the rf in input is debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, m1 on the adf4001. table v shows the truth table. fastlock enable bit db9 of the function latch is the fastlock enable bit. only when this is 1 is fastlock enabled. fastlock mode bit db10 of the function latch is the fastlock mode bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the n counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch. fastlock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the n counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determ ined by the value in tc4?c1, the cp gain bit in the n counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see table v for the timeout periods. timer counter control the user has the option of programming two charge pump currents. the intent is that the current setting 1 is used when the rf output is stable and the system is in a static state. cur- rent setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). the normal sequence of events is as follows. the user initially decides what the preferred charge pump cur- rents are going to be. for example, they may choose 2.5 ma as current setting 1 and 5 ma as current setting 2. at the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. this is controlled by the timer counter control bits db14 to db11 (tc4?c1) in the function latch. the truth table is given in table v. now, when the user wishes to program a new output frequency, they can simply program the n counter latch with new value for n. at the same time, they can set the cp gain bit to a 1, which sets the charge pump with the value in cpi6?pi4 for a period of time determined by tc4?c1. when this time is up, the charge pump current reverts to the value set by cpi3?pi1. at the same time, the cp gain bit in the n counter latch is reset to 0 and is now ready for the next time that the user wishes to change the freque ncy. note that there is an enable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit (db10) in the function latch to 1. charge pump currents cpi3, cpi2, cpi1 program current setting 1 for the charge pump. cpi6, cpi5, cpi4 program current setting 2 for the charge pump. the truth table is given in table v. pd polarity this bit sets the pd polarity bit (see table v). cp three-state t his bit sets the cp output pin. with the bit set high, the cp output is put into three-state. with the bit set low, the cp output is enabled. b
rev. adf4001 ?3 initialization latch when c2, c1 = 1, 1, the initialization latch is programmed. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed, there is an additional internal reset pulse applied to the r and n counters. this pulse ensures that the n counter is at a load point when the n counter data is latched, and the device will begin counting in close phase alignment. if the latch is programmed for synchronous power-down (the ce pin is high; pd1 bit is high; and pd2 bit is low), the internal pulse also triggers this power-down. the oscillator input buffer is unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. when the first n counter data is latched after initialization, the internal reset pulse is again activated. however, successive n counter loads will not trigger the internal reset pulse. device programming after initial power-up after initially powering up the device, there are three ways to program the device. initialization latch method apply v dd . program the initialization latch (11 in 2 lsb of input word). make sure that f1 bit is programmed to 0. do an r load (00 in 2 lsbs). do an n load (01 in 2 lsbs). when the initialization latch is loaded, the following occurs: 1. the function latch contents are loaded. 2. an internal pulse resets the r, n, and timeout counters to load state conditions and also three-states the charge pump. note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allow- ing close phase alignment when counting resumes. 3. latching the first n counter data after the initialization word will activate the same internal reset pulse. successive n loads will not trigger the internal reset pulse unless there is another initialization. ce pin method apply v dd . bring ce low to put the device into power-down. this is an asynchronous power-down in that it happens immediately. program the function latch (10). program the r counter latch (00). program the n counter latch (01). bring ce high to take the device out of power-down. the r and ab counters will now resume counting in close alignment. note that after ce goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce ca n be used to power the device up and down to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method apply v dd . do a function latch load (10 in 2 lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. do an r counter load (00 in 2 lsbs). do an n counter load (01 in 2 lsbs). do a function latch load (10 in 2 lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initial- ization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump but does not trigger synchronous power-down. the counter reset method requires an extra func- tion latch load compared to the initialization latch method. application extremely stable, low jitter reference clock for gsm base station transmitter figure 7 shows the adf4001 being used with a vcxo to pro- duce an extremely stable, low jitter reference clock for a gsm base station local oscillator (lo). r divider rf in pfd charge pump n divider 1 1 loop filter cp vcxo 13mhz system clock adf4110 adf4111 adf4112 adf4113 ref in cp rf in a loop filter vco adf4001 13mhz rf in figure 7. low jitter, stable clock source for gsm base station local oscillator circuit the system reference signal is applied to the circuit at ref in . typical gsm systems would have a very stable ocxo as the clock source for the entire base station. however, distribution of this signal around the base station makes it susceptible to noise and spurious pickup. it is also open to pulling from the various loads it may need to drive. the charge pump output of the adf4001 (pin 2 of the tssop) drives the loop filter and the 13 mhz vcxo. the vcxo output is fed back to the rf input of the adf4001 and also drives the reference (ref in ) for the lo. a t-circuit configuration pro vides 50 ? matching between the vcxo output, the lo ref in , and the rf in terminal of the adf4001. b
rev. adf4001 ?4 coherent clock generation when testing a/d converters, it is often advantageous to use a coherent test system, that is, a system that ensures a specific relationship between the a/d converter input signal and the a/ d converter sample rate. thus, when doing an fft on this data, there is no longer any need to apply the window weighting function. figure 8 shows how the adf4001 can be used to handle all the possible combinations of the input signal frequency and sampling rate. the first adf4001 is phase locked to a vco. the output of the vco is also fed into the n divider of the second adf4001. this results in both adf4001s being coherent with the ref in . since the ref in comes from the signal generator, the muxout signal of the second adf4001 is coherent with the f in frequency to the adc. this is used as f s , the sampling clock. cp rf ref in f s = (f in n 1)/(r1 n2) a/d converter under test adf4001 adf4001 sine output bruel & kjaer model 1051 square output vco 100mhz loop filter rf in rf in muxout nc7s04 n2 n1 r1 f in f s sampling clock a in figure 8. coherent clock generator tri-band clock generation circuit in multiband applications, it is necessary to realize different clocks from one master clock frequency. for example, gsm uses a 13 mhz system clock, wcdma uses 19.44 mhz, and cdma uses 19.2 mhz. the circuit in figure 9 shows how to use the adf4001 to generate gsm, wcdma, and cdma system clocks from a single 52 mhz master clock. the low rf f min specification and the ability to program r and n values as low as 1 makes the adf4001 suitable for this. other f out clock frequencies can be realized using the formula f ref n r out in = () shutdown circuit the circuit in figure 10 shows how to shut down both the adf4001 and the accompanying vco. the adg702 switch goes open circuit when a logic 1 is applied to the in input. the low cost switch is available in both sot-23 and micro soic packages. 19.44mhz system clock for wcdma 19.2mhz system clock for cdma 13mhz system clock for gsm r2 1300 adf4001 rf in ref in cp rf 65 r3 cp rf adf4001 ref in rf in r1 4 ref in rf in adf4001 cp rf 52mhz master clock n2 486 loop filter vcxo 19.44mhz n1 1 n3 24 vcxo 13mhz vcxo 19.2mhz loop filter loop filter figure 9. tri-band system clock generation fref in agnd 4 dgnd 9 cpgnd 3 adf4001 rf in a rf in b 100pf 100pf 51 av dd v dd 7 dv dd 15 v p v p 16 ce 10 1 2 r set cp power-down control decoupling capacitors and interface signals have been omitted from the diagram in the interest of greater clarity. 6 5 10k loop filter rf out 100pf 18 18 18 100pf adg702 s d gnd v dd in v cc gnd vco or vcxo figure 10. local oscillator shutdown circuit b
rev. adf4001 ?5 interfacing the adf4001 family has a simple spi compatible serial inter- face for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of sclk will be transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 833 khz or one update every 1.2 ms. this is certainly more than ad equate for systems with typical lock times in hundreds of microseconds. aduc812 interface figure 11 shows the interface between the adf4001 family and the aduc812 microconverter . since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4001 family needs a 24-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. on first applying power to the adf4001 family, it needs three writes (one each to the r counter latch, the n counter latch, and the initialization latch) for the output to become active. i/o port lines on the aduc812 are also used to control power- down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maxi- mum rate at which the output frequency can be changed will be 166 khz. aduc812 adf4001 sclk sdata le ce muxout (lock detect) sclock mosi i/o ports figure 11. aduc812 to adf4001 family interface adsp-2181 interface figure 12 shows the interface between the adf4001 family and the adsp-21xx digital signal processor. the adf4001 family needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. adf4001 sclk sdata le ce muxout (lock detect) adsp-21xx sclk i/o flags dt tfs figure 12. adsp-21xx to adf4001 family interface pcb design guidelines for chip scale package the leads on the chip package (cp-20) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the pack age lead width. the lead should be centered on the pad to ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edge of the pad pattern. this will ensure that shorting is avoided. thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the printed circuit board thermal pad to agnd. b
adf4001 rev. b | page 16 outline dimensions figure 13. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters figure 14. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm, very very thin quad (cp-20-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4001bru ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 adf4001bru-reel ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adf4001bru-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adf4001bruz ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 adf4001bruz-r7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ADF4001BRUZ-RL ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adf4001bcpz ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adf4001bcpz-rl ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 adf4001bcpz-rl7 ?40c to +85c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-6 ev-adf4001sd1z evaluation board 1 z = rohs compliant part. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd-1. bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 2.30 2.10 sq 2.00 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 08-16-2010-b
adf4001 rev. b | page 17 revision history 4/13rev. a to rev. b changed rf in a to rf in b from 320 mv to 600 mv ................ 3 updated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 16 10/03rev. 0 to rev. a changes to specifications ................................................................ 2 edits to ordering guide .................................................................. 3 changes to pin configurations ....................................................... 4 updated outline dimensions ....................................................... 16 purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02569-0-4/13(b)

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